The rest of the constant is the actual value.
A h means the number is in hex, a d means it's decimal, and b means it's binary. The second part of the constant is the base for the number. This is important because you usually want the constant's width to match the signal you are assigning it to. The first one is 8 bits, the second 5, and the third 4. In these three cases, you can tell how many bits wide each constant is by the first number. A constant looks something like 8'hD5, 5'd61, or 4'b0101. Now is a good time to introduce constants in Verilog. In this case, you can use the assign keyword. There are many times where you want to assign a value to a wire that is already declared somewhere else. We can then use rst in the rest of our design. The rst wire we declared earlier is connected to the module's output. The difference will be covered more later. For a single bit like rst_n they are interchangable. However, the ! is a logical not while the ~ is a bitwise not. Both the ! and ~ operators are defined as not (meaning inverting). The ! in front of rst_n negates it just like the ~ from before. The notable ones here are we are connecting !rst_n to in and out to rst. The name in the parenthesis is the signal we are connecting it to. The name following the period is the name of the module's port. The next part of the declaration wires up the inputs and outputs to signals in our design.
Just name it something descriptive so the hierarchy of your project is easy to understand. Using the same name for the instance and the module type is common when you only have one instance of it. The name you give the instance isn't particularly important. The first reset_conditioner is the name of the module we want to instantiate, the second reset_conditioner is the name of this particular instance.
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